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Asic Design Engineers
Attn: je0107

Bring your high speed RISC ideas to one of the fastest, successful, and profitable San Francisco Bay Area Companies.
Duties Involve: Design from cradle to grave ( Concept to Manufacturing ) a high speed, high-quality image, RISC based system. A Verilog synopsis environment.

Skill Set: Graphic Video, Printing, Asic & FPGA.
Attn: je1025

Define architecture from concept through manufacturing for the next generation networking chip. Good understanding of the big picture.

Skill Set: RTL verification, simulation, Verilog and Synopsis environment. ASIC, Perl and C.
Attn: je0116

High equity startup seeks top notch ASIC designers. To design a low power, high speed chip. Skill Set: Verilog, Synopsis, static timing, and MPEG2 Video.

Skill Set: RISC CPU, PCI, graphics and C.
Attn: je0126

Sr. Asic Design Engineer: Bring your high-speed, T1/E1 ethernet application skills to a leader in the communication industry. A mid sized, financially stable, secure and fast growing company.

Responsibility: Define, architect, and design a large communication chip.Carry out the multi-stage development through specification, testing, verification, backend validation, simulation and implementation of algorithms.

Skill Set: VHDL,Synopsis, RTL simulation and algorithm development.
Attn: je0127

Become part of an elite team in one of the most profitable and successful San Fancisco Bay Companies. Design from cradle to grave a high-speed RISC-based system. A high performance state of the art communication chip.

Skill Set: Top-Notch Hardware Designer with knowledge of Verilog, Synopsys, Cadence, ASIC, FPGA and great communication skills.
Attn: je0130

Design a programmable audio chip for the next generation.AC3/MPEG decoder. Design and develop a complex DSP audiochip. Perform product verification, place and route, and algorithm development.

Skill Set: Chip Level Logic Design, Place and Route, Clock Issues, DSP, Audio, AC3 and MPEG decoder
Attn: je0129

Bring your high speed RISC ideas to one of the fastest, successful and profitable San Francisco Bay Area Companies.
Duties Involve: Design from cradle to grave (Concept to Manufacturing ) a high-speed, high-quality, image RISC based system. A Verilog, Synopsis environment.

Skill Set: Graphic Video, printing, Asic and FPGA.
Attn: je0160

A chance to be part of a network company doing voice-over-IP (VOIP) Duties Involve: Chip implementation, verification, ASIC design using Verilog and C.

Skill Set: Chip design methodology, physical implementation, DSP, networking and telecommunication experience, synthesis and timing flow.
Attn: je0169

Unique opportunity to develop advanced ASICs for high performance network switches and routers. This involves 10 Gigabit Ethernet devices.

Skill Set: Extensive use of Verilog HDL design and simulation tools. Static timing analysis and synthesis. Knowledge of Ethernet MAC/PCS/IPX and network protocols. Know bridges, switches and routers, formal verification and verification methodologies.
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